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Features
* EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, * * * * * * * * * * *
2,097,152 x 1-, and 4,194,304 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) Supports both 3.3V and 5.0V Operating Voltage Applications In-System Programmable (ISP) via Two-Wire Bus Simple Interface to SRAM FPGAs Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX(R), APEXTM Devices, Lucent ORCA(R), Xilinx XC3000TM, XC4000TM, XC5200TM, Spartan(R), Virtex(R) FPGAs Cascadable Read-back to Support Additional Configurations or Higher-density Arrays Very Low-power CMOS EEPROM Process Programmable Reset Polarity Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC Packages), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC, 44-lead PLCC and 44-lead TQFP Packages Emulation of Atmel's AT24CXXX Serial EEPROMs Low-power Standby Mode High-reliability - Endurance: 100,000 Write Cycles - Data Retention: 90 Years for Industrial Parts (at 85C) and 190 Years for Commercial Parts (at 70C)
FPGA Configuration EEPROM Memory AT17LV65 AT17LV128 AT17LV256 AT17LV512 AT17LV010 AT17LV002 AT17LV040 3.3V and 5V System Support
Description
The AT17LV series FPGA Configuration EEPROMs (Configurators) provide an easyto-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17LV series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20lead PLCC, 20-lead SOIC, 44-lead PLCC and 44-lead TQFP, see Table 1. The AT17LV series Configurators uses a simple serial-access procedure to configure one or more FPGA devices. The user can select the polarity of the reset function by programming four EEPROM bytes. These devices also support a write-protection mechanism within its programming mode. The AT17LV series configurators can be programmed with industry-standard programmers, Atmel's ATDH2200E Programming Kit or Atmel's ATDH2225 ISP Cable. Table 1. AT17LV Series Packages
AT17LV65/ AT17LV128/ AT17LV256 Yes Yes Yes Yes Yes(2) - - AT17LV512/ AT17LV010 Yes Yes Use 8-lead LAP Yes Yes(2) - -
(1)
Package 8-lead LAP 8-lead PDIP 8-lead SOIC 20-lead PLCC 20-lead SOIC 44-lead PLCC 44-lead TQFP Notes:
AT17LV002 Yes - Use 8-lead LAP Yes Yes(2) Yes Yes
(1)
AT17LV040
(3)
-
(3)
- - Yes Yes
1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8lead SOIC package is not available for the AT17LV512/010/002 devices, it is possible to use an 8-lead LAP package instead. 2. The pinout for the AT17LV65/128/256 devices is not pin-for-pin compatible with the AT17LV512/010/002 devices. 3. Refer to the AT17Fxxx datasheet, available on the Atmel web site.
Rev. 2321E-CNFG-06/03
1
Pin Configuration
8-lead LAP
DATA CLK (1) (WP ) RESET/OE CE
1 2 3 4
8 7 6 5
VCC SER_EN CEO (A2) GND
8-lead SOIC
DATA CLK (1) (WP ) RESET/OE CE
1 2 3 4
8 7 6 5
VCC SER_EN CEO (A2) GND
8-lead PDIP
DATA CLK (WP(1)) RESET/OE CE
1 2 3 4
8 7 6 5
VCC SER_EN CEO (A2) GND
20-lead PLCC
NC DATA NC VCC NC 3 2 1 20 19 NC GND NC NC NC 9 10 11 12 13
CLK (WP1(2)) NC (WP(1)) RESET/OE (WP2(2)) NC CE
4 5 6 7 8
18 17 16 15 14
NC SER_EN NC NC (READY(2)) CEO (A2)
Notes:
1. This pin is only available on AT17LV65/128/256 devices. 2. This pin is only available on AT17LV512/010/002 devices.
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AT17LV65/128/256/512/010/002/040
20-lead SOIC(1)
NC DATA NC CLK NC RESET/OE NC CE NC GND
Note:
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC NC NC SER_EN NC NC CEO (A2) NC NC NC
1. This pinout only applies to AT17LV65/128/256 devices.
20-lead SOIC(1)
DATA NC CLK NC NC NC NC RESET/OE NC CE
Note:
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC NC SER_EN NC NC NC NC CEO NC GND
1. This pinout only applies to AT17LV512/010/002 devices.
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44 PLCC
NC CLK NC NC DATA NC VCC NC NC SER_EN NC
44 43 42 41 40 39 38 37 36 35 34 NC CLK NC NC DATA NC VCC NC NC SER_EN NC
NC RESET/OE NC CE NC NC GND NC NC CEO/A2 NC
18 19 20 21 22 23 24 25 26 27 28
(WP1(1)) NC NC NC NC NC NC NC NC NC NC NC
6 5 4 3 2 1 44 43 42 41 40
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36 35 34 33 32 31 30 29
NC NC NC NC NC NC NC NC NC NC READY
44 TQFP
NC NC NC NC NC NC (WP1(1)) NC NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11
12 13 14 15 16 17 18 19 20 21 22
33 32 31 30 29 28 27 26 25 24 23
NC NC NC NC NC NC NC NC NC NC READY
Note:
1. This pin is only available on AT17LV002 devices.
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AT17LV65/128/256/512/010/002/040
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NC RESET/OE NC CE NC NC GND NC NC CEO(A2) NC
AT17LV65/128/256/512/010/002/040
Block Diagram
SER_EN WP1(2) WP2(2)
POWER ON RESET
READY
(2)
(1)
Notes:
1. This pin is only available on AT17LV65/128/256 devices. 2. This pin is only available on AT17LV512/010/002 devices.
Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration EEPROM without requiring an external intelligent controller. The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven High, the configuration EEPROM resets its address counter and tri-states its DATA pin. The CE pin also controls the output of the AT17LV series configurator. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tristated. When OE is subsequently driven Low, the counter and the DATA output pin are enabled. When RESET/OE is driven High again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE. When the configurator has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset. This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High, this document will describe RESET/OE. 5
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Pin Description
AT17LV65/ AT17LV128/ AT17LV256 8 DIP/ LAP/ SOIC 1 2 - 3 8 DIP/ LAP 1 2 - 3 - 4 5 O 6 A2 READY SER_EN VCC I O I - 7 8 - 17 20 - 17 20 - 7 8 15 17 20 14 14 6 14 - - 18 20 - 7 8 15 17 20 8 10 8 10 4 5 AT17LV512/ AT17LV010 8 DIP/ LAP/ SOIC 1 2 - 3 - 4 5 6 AT17LV002 AT17LV040
Name DATA CLK WP1 RESET/OE WP2 CE GND CEO
I/O I/ O I I I I I
20 PLCC 2 4 - 6
20 SOIC 2 4 - 6
20 PLCC 2 4 5 6 7 8 10
20 SOIC 1 3 - 8 - 10 11 13
20 PLCC 2 4 5 6 7 8 10 14
20 SOIC 1 3 - 8 - 10 11 13
44 PLCC 2 5 - 19 - 21 24 27
44 TQFP 40 43 - 13 - 15 18 21 23 35 38
44 PLCC 2 5 - 19 - 21 24 27 29 41 44
44 TQFP 40 43 - 13 - 15 18 21 23 35 38
- - 18 20 29 41 44
DATA CLK WP1
Three-state DATA output for configuration. Open-collector bi-directional pin for programming. Clock input. Used to increment the internal address and bit counter for reading and programming. WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled by default due to internal pull-down resistor. This input pin is not used during FPGA loading operations. This pin is only available on AT17LV512/010/002 devices. Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the data output driver. The logic polarity of this input is programmable as either RESET/OE or RESET/OE. For most applications, RESET should be programmed active Low. This document describes the pin as RESET/OE. Write protect (WP) input (when CE is Low) during programming only (SER_EN Low). When WP is Low, the entire memory can be written. When WP is enabled (High), the lowest block of the memory cannot be written. This pin is only available on AT17LV65/128/256 devices. WRITE PROTECT (2). Used to protect portions of memory during programming. Disabled by default due to internal pull-down resistor. This input pin is not used during FPGA loading operations. This pin is only available on AT17LV512/010 devices.
RESET/OE
WP
WP2
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AT17LV65/128/256/512/010/002/040
CE
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address counter and enables the data output driver. A High level on CE disables both the address and bit counters and forces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the Two-Wire Serial Programming mode (SER_EN Low). Ground pin. A 0.2 F decoupling capacitor between VCC and GND is recommended. Chip Enable Output (active Low). This output goes Low when the address counter has reached its maximum value. In a daisy chain of AT17LV series devices, the CEO pin of one device must be connected to the CE input of the next device in the chain. It will stay Low as long as CE is Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay High until the entire EEPROM is read again. Device selection input, A2. This is used to enable (or select) the device during programming (i.e., when SER_EN is Low). A2 has an internal pull-down resistor. Open collector reset state indicator. Driven Low during power-up reset, released when power-up is complete. It is recommended to use a 4.7 k pull-up resistor when this pin is used. Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low enables the Two-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to VCC. 3.3V (10%) and 5.0V (5% Commercial, 10% Industrial) power supply pin.
GND CEO
A2 READY
SER_EN
VCC
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FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory. The AT17LV Serial Configuration EEPROM has been designed for compatibility with the Master Serial mode. This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xilinx applications.
Control of Configuration
Most connections between the FPGA device and the AT17LV Serial EEPROM are simple and self-explanatory. * * * * * The DATA output of the AT17LV series configurator drives DIN of the FPGA devices. The master FPGA CCLK output drives the CLK input of the AT17LV series configurator. The CEO output of any AT17LV series configurator drives the CE input of the next configurator in a cascaded chain of EEPROMs. SER_EN must be connected to VCC (except during ISP). The READY(1) pin is available as an open-collector indicator of the device's reset status; it is driven Low while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete.
1. This pin is not available for the AT17LV65/128/256 devices.
Note:
Cascading Serial Configuration EEPROMs
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories, cascaded configurators provide additional memory. After the last bit from the first configurator is read, the clock signal to the configurator asserts its CEO output Low and disables its DATA line driver. The second configurator recognizes the Low level on its CE input and enables its DATA output. After configuration is complete, the address counters of all cascaded configurators are reset if the RESET/OE on each configurator is driven to its active (Low) level. If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to its inactive (High) level.
AT17LV Series Reset Polarity Programming Mode
The AT17LV series configurator allows the user to program the reset polarity as either RESET/OE or RESET/OE. This feature is supported by industry-standard programmer algorithms. The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the Two-Wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated inside the chip. The AT17LV series configurators enter a low-power standby mode whenever CE is asserted High. In this mode, the AT17LV65/128/256 configurator consumes less than 50 A of current at 3.3V (100 A for the AT17LV512/010 and 200 A for the AT17LV002/040). The output remains in a high-impedance state regardless of the state of the OE input.
Standby Mode
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AT17LV65/128/256/512/010/002/040
Absolute Maximum Ratings*
Operating Temperature.................................... -40C to +85C Storage Temperature ..................................... -65 C to +150C Voltage on Any Pin with Respect to Ground ..............................-0.1V to VCC +0.5V Supply Voltage (VCC) .........................................-0.5V to +7.0V Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260C ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.
Operating Conditions
3.3V Symbol Description Commercial VCC Industrial Supply voltage relative to GND -0C to +70C Supply voltage relative to GND -40C to +85C Min 3.0 3.0 Max 3.6 3.6 Min 4.75 4.5 5V Max 5.25 5.5 Units V V
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DC Characteristics
VCC = 3.3V 10%
AT17LV65/ AT17LV128/ AT17LV256 Symbol VIH VIL VOH VOL VOH VOL ICCA IL ICCS Description High-level Input Voltage Low-level Input Voltage High-level Output Voltage (IOH = -2.5 mA) Low-level Output Voltage (IOL = +3 mA) High-level Output Voltage (IOH = -2 mA) Low-level Output Voltage (IOL = +3 mA) Supply Current, Active Mode Input or Output Leakage Current (VIN = VCC or GND) Commercial Supply Current, Standby Mode Industrial 100 100 150 A -10 2.4 Industrial 0.4 5 10 50 -10 0.4 5 10 100 -10 0.4 5 10 150 V mA A A Commercial 0.4 2.4 0.4 2.4 0.4 V V Min 2.0 0 2.4 Max VCC 0.8 AT17LV512/ AT17LV010 Min 2.0 0 2.4 Max VCC 0.8 AT17LV002/ AT17LV040 Min 2.0 0 2.4 Max VCC 0.8 Units V V V
DC Characteristics
VCC = 5V 5% Commercial; VCC = 5V 10% Industrial
AT17LV65/ AT17LV128/ AT17LV256 Symbol VIH VIL VOH VOL VOH VOL ICCA IL ICCS Description High-level Input Voltage Low-level Input Voltage High-level Output Voltage (IOH = -2.5 mA) Low-level Output Voltage (IOL = +3 mA) High-level Output Voltage (IOH = -2 mA) Low-level Output Voltage (IOL = +3 mA) Supply Current, Active Mode Input or Output Leakage Current (VIN = VCC or GND) Commercial Supply Current, Standby Mode Industrial 150 200 350 A -10 3.6 Industrial 0.37 10 10 75 -10 0.37 10 10 200 -10 0.37 10 10 350 V mA A A Commercial 0.32 3.76 0.32 3.76 0.32 V V Min 2.0 0 3.7 Max VCC 0.8 AT17LV512/ AT17LV010 Min 2.0 0 3.86 Max VCC 0.8 AT17LV002/ AT17LV040 Min 2.0 0 3.86 Max VCC 0.8 Units V V V
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AT17LV65/128/256/512/010/002/040
AC Characteristics
CE TSCE RESET/OE TLC CLK TOE TCE DATA TOH TCAC TOH TDF THC THOE TSCE THCE
AC Characteristics when Cascading
RESET/OE
CE
CLK TCDF DATA
LAST BIT FIRST BIT
TOCK CEO
TOCE
TOOE
TOCE
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AC Characteristics
VCC = 3.3V 10%
AT17LV65/128/256 Commercial Symbol TOE(1) TCE(1) TCAC TOH TDF(2) TLC THC TSCE THCE THOE FMAX
(1)
AT17LV512/010/002/040 Commercial Min Max 50 55 55 0 55 50 25 25 30 0 25 10 15 25 25 35 0 25 10 0 50 Industrial Min Max 55 60 60 Units ns ns ns ns ns ns ns ns ns ns MHz
Industrial Min Max 55 60 80 0
Description OE to Data Delay CE to Data Delay CLK to Data Delay Data Hold from CE, OE, or CLK CE or OE to Data Float Delay CLK Low Time CLK High Time CE Setup Time to CLK (to guarantee proper counting) CE Hold Time from CLK (to guarantee proper counting) OE High Time (guarantees counter is reset) Maximum Clock Frequency
Min
Max 50 60 75
0 55 25 25 35 0 25 10
25 25 60 0 25
Notes:
1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
AC Characteristics when Cascading
VCC = 3.3V 10%
AT17LV65/128/256 Commercial Symbol TCDF
(2) (1) (1) (1)
AT17LV512/010/002/040 Commercial Min Max 50 50 35 35 12.5 Industrial Min Max 50 55 40 35 10 Units ns ns ns ns MHz
Industrial Min Max 60 60 60 45 8
Description CLK to Data Float Delay CLK to CEO Delay CE to CEO Delay RESET/OE to CEO Delay Maximum Clock Frequency
Min
Max 60 55 55 40 8
TOCK TOCE
TOOE FMAX
Notes:
1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
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AT17LV65/128/256/512/010/002/040
AC Characteristics
VCC = 5V 5% Commercial; VCC = 5V 10% Industrial
AT17LV65/128/256 Commercial Symbol TOE TCE
(1) (1) (1)
AT17LV512/010/002/040 Commercial Min Max 30 45 50 0 50 50 20 20 20 0 20 12.5 15 20 20 25 0 20 15 0 50 Industrial Min Max 35 45 50 Units ns ns ns ns ns ns ns ns ns ns MHz
Industrial Min Max 35 45 55 0
Description OE to Data Delay CE to Data Delay CLK to Data Delay Data Hold from CE, OE, or CLK CE or OE to Data Float Delay CLK Low Time CLK High Time CE Setup Time to CLK (to guarantee proper counting) CE Hold Time from CLK (to guarantee proper counting) OE High Time (guarantees counter is reset) Maximum Clock Frequency
Min
Max 30 45 50
TCAC TOH TDF TLC THC TSCE
0 50 20 20 35 0 20 12.5
(2)
20 20 40 0 20
THCE THOE FMAX
Notes:
1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
AC Characteristics when Cascading
VCC = 5V 5% Commercial; VCC = 5V 10% Industrial
AT17LV65/128/256 Commercial Symbol TCDF
(2) (1) (1) (1)
AT17LV512/010/002/040 Commercial Min Max 50 35 35 30 12.5 Industrial Min Max 50 40 35 30 12.5 Units ns ns ns ns MHz
Industrial Min Max 50 40 35 35 10
Description CLK to Data Float Delay CLK to CEO Delay CE to CEO Delay RESET/OE to CEO Delay Maximum Clock Frequency
Min
Max 50 35 35 30 10
TOCK TOCE
TOOE FMAX
Notes:
1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
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Thermal Resistance Coefficients(1)
Package Type 8CN4 Leadless Array Package (LAP) AT17LV65/ AT17LV128/ AT17LV256 AT17LV512/ AT17LV010 45 135.71 37 107 - - 35 90 AT17LV002 45 159.60 - - - - 35 90 AT17LV040 - - - - - - - - - - - - - - - - - - 17 62 15 50 17 62 15 50
JC [C/W] JA [C/W]
(2)
45 115.71 37 107 45 150 35 90
8P3
Plastic Dual Inline Package (PDIP) Plastic Gull Wing Small Outline (SOIC) Plastic Leaded Chip Carrier (PLCC) Plastic Gull Wing Small Outline (SOIC) Thin Plastic Quad Flat Package (TQFP) Plastic Leaded Chip Carrier (PLCC)
JC [C/W] JA [C/W]
(2)
8S1
JC [C/W] JA [C/W]
(2)
20J
JC [C/W] JA [C/W]
(2)
20S2
JC [C/W] JA [C/W]
(2)
44A
JC [C/W] JA [C/W]
(2)
44J
JC [C/W] JA [C/W]
(2)
Notes:
1. For more information refer to the "Thermal Characteristics of Atmel's Packages", available on the Atmel web site. 2. Airflow = 0 ft/min.
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Figure 1. Ordering Code
AT17LV65A-10PC
Voltage 3.0V to 5.5V
Size (Bits) 65 128 256 512 010 002 040 = 65K = 128K = 256K = 512K = 1M = 2M = 4M
Special Pinouts A = Altera
Package C P N J S
Temperature
= 8CN4 C = Commercial = 8P3 = 8S1 = 20J = 20S2 I = Industrial
Blank = Xilinx /Atmel/ Other
TQ = 44A BJ = 44J
Package Type 8CN4 8P3 8S1 20J 20S2 44A 44J 8-lead, 6 mm x 6 mm x 1 mm, Leadless Array Package (LAP) - Pin-compatible with 8-lead SOIC/VOID Packages 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 20-lead, Plastic J-leaded Chip Carrier (PLCC) 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP) 44-lead, Plastic J-leaded Chip Carrier (PLCC)
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Ordering Information
Memory Size 64-Kbit
(1)
Ordering Code AT17LV65-10CC AT17LV65-10PC AT17LV65-10NC AT17LV65-10JC AT17LV65-10SC AT17LV65-10CI AT17LV65-10PI AT17LV65-10NI AT17LV65-10JI AT17LV65-10SI
Package 8CN4 8P3 8S1 20J 20S2 8CN4 8P3 8S1 20J 20S2 8CN4 8P3 8S1 20J 20S2 8CN4 8P3 8S1 20J 20S2 8CN4 8P3 8S1 20J 20S2 8CN4 8P3 8S1 20J 20S2 8CN4 8P3 20J 20S2 8CN4 8P3 20J 20S2 8CN4 8P3 20J 20S2 8CN4 8P3 20J 20S2 8CN4 20J 20S2 44A 44J 8CN4 20J 20S2 44A 44J 44A 44J 44A 44J
Operation Range Commercial (0C to 70C)
Industrial (-40C to 85C)
128-Kbit(1)
AT17LV128-10CC AT17LV128-10PC AT17LV128-10NC AT17LV128-10JC AT17LV128-10SC AT17LV128-10CI AT17LV128-10PI AT17LV128-10NI AT17LV128-10JI AT17LV128-10SI
Commercial (0C to 70C)
Industrial (-40C to 85C)
256-Kbit(1)
AT17LV256-10CC AT17LV256-10PC AT17LV256-10NC AT17LV256-10JC AT17LV256-10SC AT17LV256-10CI AT17LV256-10PI AT17LV256-10NI AT17LV256-10JI AT17LV256-10SI
Commercial (0C to 70C)
Industrial (-40C to 85C)
512-Kbit(1)
AT17LV512-10CC AT17LV512-10PC AT17LV512-10JC AT17LV512-10SC AT17LV512-10CI AT17LV512-10PI AT17LV512-10JI AT17LV512-10SI
Commercial (0C to 70C)
Industrial (-40C to 85C)
1-Mbit(1)
AT17LV010-10CC AT17LV010-10PC AT17LV010-10JC AT17LV010-10SC AT17LV010-10CI AT17LV010-10PI AT17LV010-10JI AT17LV010-10SI
Commercial (0C to 70C)
Industrial (-40C to 85C)
2-Mbit(1)
AT17LV002-10CC AT17LV002-10JC AT17LV002-10SC AT17LV002-10TQC AT17LV002-10BJC AT17LV002-10CI AT17LV002-10JI AT17LV002-10SI AT17LV002-10TQI AT17LV002-10BJI
Commercial (0C to 70C)
Industrial (-40C to 85C)
4-Mbit(1)
AT17LV040-10TQC AT17LV040-10BJC AT17LV040-10TQI AT17LV040-10BJI
Commercial (0C to 70C) Industrial (-40C to 85C)
Note:
1. For operating 5V operating voltage, please refer to the corresponding AC and DC Characteristics.
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AT17LV65/128/256/512/010/002/040
Packaging Information
8CN4 - LAP
Marked Pin1 Indentifier
E
D
A A1
Top View
0.10 mm TYP
Side View
L1
Pin1 Corner
8
1
e
7 2
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 0.94 0.30 0.45 5.89 4.89 NOM 1.04 0.34 0.50 5.99 5.99 1.27 BSC 1.10 REF 0.95 1.25 1.00 1.30 1.05 1.35 1 1 MAX 1.14 0.38 0.55 6.09 6.09 1 NOTE
6
3
A
b
5 4
A1 b D E
e1
L
e e1 L L1
Bottom View
Note: 1. Metal Pad Dimensions.
11/14/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 8CN4, 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm, Leadless Array Package (LAP) DRAWING NO. 8CN4 REV. A
R
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8P3 - PDIP
E E1
1
N
Top View
c eA
End View
D e D1 A2 A
SYMBOL
COMMON DIMENSIONS (Unit of Measure = inches) MIN NOM MAX NOTE
A A2 b b2 b3 c D 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.310 0.250 0.100 BSC 0.300 BSC 0.115 0.130 0.130 0.018 0.060 0.039 0.010 0.365
0.210 0.195 0.022 0.070 0.045 0.014 0.400
2
5 6 6
3 3
b2 b3
4 PLCS
L
D1 E E1 e eA L
b
0.325 0.280
4 3
Side View
4 0.150 2
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B
R
18
AT17LV65/128/256/512/010/002/040
2321E-CNFG-06/03
AT17LV65/128/256/512/010/002/040
8S1 - SOIC
3
2
1
H
N
Top View
e B A
D
Side View
SYMBOL A
COMMON DIMENSIONS (Unit of Measure = mm) MIN - - - - - NOM - - - - - 1.27 BSC - - - - 6.20 1.27 MAX 1.75 0.51 0.25 5.00 4.00 NOTE
A2
C
B C D E
L E
e H L
End View
Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.
10/10/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. A
R
19
2321E-CNFG-06/03
20J - PLCC
1.14(0.045) X 45
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45
0.318(0.0125) 0.191(0.0075)
e E1 B E B1 D2/E2
D1 D A
A2 A1
0.51(0.020)MAX 45 MAX (3X)
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 9.779 8.890 9.779 8.890 7.366 0.660 0.330 NOM - - - - - - - - - - 1.270 TYP MAX 4.572 3.048 - 10.033 9.042 10.033 9.042 8.382 0.813 0.533 Note 2 Note 2 NOTE
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 20J REV. B
R
20
AT17LV65/128/256/512/010/002/040
2321E-CNFG-06/03
AT17LV65/128/256/512/010/002/040
20S2 - SOIC
C
1
EH
N
Top View
A1
End View
COMMON DIMENSIONS (Unit of Measure = inches)
e
b A D
SYMBOL
MIN
L
NOM
MAX
NOTE
A A1 b C D
0.0926 0.0040 0.0130 0.0091 0.4961 0.2914 0.3940 0.0160 0.050 BSC
0.1043 0.0118 0.0200 0.0125 0.5118 0.2992 0.4190 0.050 3 1 2 4
Side View
E H L e
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information. 2. Dimension "D" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006") per side. 3. Dimension "E" does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010") per side. 4. "L" is the length of the terminal for soldering to a substrate. 5. The lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm 1/9/02 (0.024") per side.
R
2325 Orchard Parkway San Jose, CA 95131
TITLE 20S2, 20-lead, 0.300" Wide Body, Plastic Gull Wing Small Outline Package (SOIC)
DRAWING NO. 20S2
REV. A
21
2321E-CNFG-06/03
44A - TQFP
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 11.75 9.90 11.75 9.90 0.30 0.09 0.45 NOM - - 1.00 12.00 10.00 12.00 10.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 12.25 10.10 12.25 10.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 44A REV. B
R
22
AT17LV65/128/256/512/010/002/040
2321E-CNFG-06/03
AT17LV65/128/256/512/010/002/040
44J - PLCC
1.14(0.045) X 45
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45 0.318(0.0125) 0.191(0.0075)
E1 B
E
B1
D2/E2
e D1 D A A2 A1
0.51(0.020)MAX 45 MAX (3X)
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 17.399 16.510 17.399 16.510 14.986 0.660 0.330 NOM - - - - - - - - - - 1.270 TYP MAX 4.572 3.048 - 17.653 16.662 17.653 16.662 16.002 0.813 0.533 Note 2 Note 2 NOTE
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 44J REV. B
R
23
2321E-CNFG-06/03
Atmel Corporation
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Available on web site
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. (c) Atmel Corporation 2003. All rights reserved. Atmel (R) and combinations thereof are the registered trademark of Atmel. FLEX TM is the trademark of Altera Corporation; ORCATM is the trademark of Lattice Semiconductors; SPARTAN (R) and Virtex (R) are the registered trademarks of Xilinx, Inc.; XC3000 TM, XC4000 TM and XC5200 TM are the trademarks of Xilinx, Inc.; APEX TM is the trademark of MIPS Technologies; Other terms and product names may be the trademarks of others.
Printed on recycled paper.
2321E-CNFG-06/03 xM

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